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| the MC88LV915T clock driver utilizes phaselocked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. it is designed to provide clock distribution for high performance pc's and workstations. the pll allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. the pll also allows the MC88LV915T to multiply a low frequency input clock and distribute it locally at a higher (2x) system frequency. multiple 88lv915's can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see figure 4 on page 9). five aqo outputs (q0q4) are provided with less than 500 ps skew between their rising edges. the q5 output is inverted (180 phase shift) from the aqo outputs. the 2x_q output runs at twice the aqo output frequency, while the q/2 runs at 1/2 the aqo frequency. the vco is designed to run optimally between 20 mhz and the 2x_q f max specification. the wiring diagrams in figure 2 detail the different feedback configurations which create specific input/output frequency relationships. possible frequency ratios of the aqo outputs to the sync input are 2:1, 1:1, and 1:2. the freq_sel pin provides one bit programmable divideby in the feedback path of the pll. it selects between divideby1 and divideby2 of the vco before its signal reaches the internal clock distribution section of the chip (see the block diagram on page 2). in most applications freq_sel should be held high ( 1). if a low frequency reference clock input is used, holding freq_sel low ( 2) will allow the vco to run in its optimal range (>20mhz). in normal phaselocked operation the pll_en pin is held high. pulling the pll_en pin low disables the vco and puts the 88lv915t in a static atest modeo. in this mode there is no frequency limitation on the input clock, which is necessary for a lo w frequency board test environment. the second sync input can be used as a test clock input to further simplify boardlevel testi ng (see detailed description on page 11). pulling the oe /rst pin low puts the clock outputs 2x_q, q0q4, q5 and q/2 into a high impedance state (3state). after the oe /rst pin goes back high q0q4, q5 and q/2 will be reset in the low state, with 2x_q being the inverse of the selected sync input. assuming pll_en is low, the outputs will remain reset until the 88lv915 sees a sync input pulse. a lock indicator output (lock) will go high when the loop is in steadystate phase and frequency lock. the lock output will go low if phaselock is lost or when the pll_en pin is low. the lock output will go high no later than 10ms after the 88lv915 sees a sync signal and full 5v v cc . features ? five outputs (q0q4) with outputoutput skew < 500 ps each being phase and frequency locked to the sync input ? the phase variation from parttopart between the sync and feedback inputs is less than 550 ps (derived from the t pd specification, which defines the parttopart skew) ? input/output phaselocked frequency ratios of 1:2, 1:1, and 2:1 are available ? input frequency range from 5mhz 2x_q fmax spec. ? additional outputs available at 2x and +2 the system aqo frequency. also a q (180 phase shift) output available ? all outputs have 36 ma drive (equal high and low) at cmos levels, and can drive either cmos or ttl inputs. all inputs are ttllevel compatible. 88ma i ol /i oh specifications guarantee 50 w transmission line switching on the incident edge ? test mode pin (pll_en) provided for low frequency testing. two selectable clock inputs for test or redundancy purposes. all outputs can go into high impedance (3state) for board test purposes ? lock indicator (lock) accuracy indicates a phaselocked state yield surface modeling and ysm are trademarks of motorola, inc. order number: MC88LV915T/d rev 3, 08/2001 semiconductor technical data ? motorola, inc. 2001 low skew cmos pll clock driver f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2 motorola %!!2# # & + & # '&2(! !$ # & + & # & ' ## + # (.#0 1 (.#0 1 ' 2(! -2& $ '() + + & & # pinout: 28lead plcc (top view) '787b7>57 5=?5< ;>@ed '787b7>57 5=?5< ;>@ed :??c7c b787b7>57 47dg77> ci>50 1 (i>50 1 ?e4=7c +$ >d7b>3= b7ae7>5i =?g 776435< ;>@ed d? @:3c7 67d75d?b >@ed 8?b 7hd7b>3= ' >7dg?b< =?5< ?ed@ed =?5<76 d? ci>5 >f7bc7 ?8 5=?5< ?ed@ed h 5=?5< ?ed@ed & 8b7ae7>5i ci>5:b?>?ec =?5< ?ed@ed& 8b7ae7>5i ci>5:b?>?ec >6;53d7c @:3c7 =?5< :3c 477> 35:;7f76 :;9: g:7> =?5<76 $ed@ed >34=7 ci>5:b?>?ec b7c7d 35d;f7 =?g ;c34=7c @:3c7=?5< 8?b =?g 8b7a d7cd;>9 %?g7b 3>6 9b?e>6 @;>c >?d7 @;>c 3b7 k3>3=?9 ce@@=i @;>c 8?b ;>d7b>3= %!! ?>=i >@ed >@ed >@ed >@ed >@ed >@ed $ed@ed $ed@ed $ed@ed $ed@ed $ed@ed >@ed >@ed pin summary (.#0 1 (.#0 1 ' 2(! '&2(! ' & & h2& & !$ $ '() %!!2# + # 03 *2- :2 :3,9043 fn suffix plastic plcc case 77602 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3 motorola MC88LV915T block diagram " * - " * - "*- %!!2# ' ' ' ' ' ' ' $ '() & & % & & & % & % -)'#! ' #),$' ' %;> ' 2(! (.# (.# ' %*"% !$$% !)' + . ),$ & & % & & & h2& & % & % & & % '&2(! $( !!)$' +$!) $#)'$!! % ( '& ))$' !$ f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4 motorola maximum ratings* symbol parameter limits unit v cc , av cc dc supply voltage referenced to gnd 0.5 to 7.0 v v in dc input voltage (referenced to gnd) 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature 65 to +150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to th e recommended operating conditions. recommended operating conditions symbol parameter limits unit v cc supply voltage 3.3 0.3 v v in dc input voltage 0 to v cc v v out dc output voltage 0 to v cc v t a ambient operating temperature 0 to 70 c esd static discharge voltage > 1000 v dc characteristics (t a = 0 c to 70 c; v cc = 3.3v 0.3v) symbol parameter v cc guaranteed limits unit condition v ih minimum high level input voltage 3.0 3.3 2.0 2.0 v v out = 0.1v or v cc 0.1v v il minimum low level input voltage 3.0 3.3 0.8 0.8 v v out = 0.1v or v cc 0.1v v oh minimum high level output voltage 3.0 3.3 2.4 2.7 v v in = v ih or v il i oh = 24ma v ol minimum low level output voltage 3.0 3.3 0.44 0.44 v v in = v ih or v il i oh = 24ma i in maximum input leakage current 3.6 1.0 m a v i = v cc , gnd i cct maximum i cc /input 3.6 2.0 ma v i = v cc 2.1v i old minimum dynamic 3 output current 3.6 +50 ma v old = 1.25v i ohd 3.6 50 ma v ohd =2.35v i cc maximum quiescent supply current 3.6 tbd m a v i = v cc , gnd 1. i ol is +12ma for the rst _out output. 2. the pll_en input pin is not guaranteed to meet this specification. 3. maximum test duration 2.0ms, one output loaded at a time. sync input timing requirements symbol parameter minimum maximum unit t rise/fall sync input rise/fall time, sync input from 0.8v to 2.0v e 5.0 ns t cycle , sync input input clock period sync input 1 f 2x_q 4 100 ns duty cycle duty cycle, sync input 50% 25% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 5 motorola frequency specifications (t a = 0 c to 70 c; v cc = 3.3v 0.3v) symbol parameter guaranteed minimum unit fmax (2x_q) maximum operating frequency, 2x_q output 100 mhz fmax (`q') maximum operating frequency, q0q3 outputs 50 mhz note: maximum operating frequency is guaranteed with the 88lv926 in a phaselocked condition. ac characteristics (t a =0 c to +70 c, v cc = 3.3v 0.3v, load = 50 w terminated to v cc /2) symbol parameter min max unit condition t rise/fall outputs rise/fall time, all outputs (between 0.8 to 2.0v) 0.5 2.0 ns into a 50 w load terminated to v cc /2 t pulse width (q0q4, q5 , q/2) output pulse width: q0, q1, q2, q3, q4, q5 , q/2 @ v cc /2 0.5t cycle 0.5 1 0.5t cycle + 0.5 1 ns into a 50 w load terminated to v cc /2 t pulse width (2x_q output) output pulse width: 40mhz 2x_q @ 1.5v 66mhz 80mhz 100mhz 0.5t cycle 1.5 0.5t cycle 1.0 0.5t cycle 1.0 0.5t cycle 1.0 0.5t cycle + 0.5 0.5t cycle + 0.5 0.5t cycle + 0.5 0.5t cycle + 0.5 ns into a 50 w load terminated to v cc /2 t cycle (2x_q output) cycletocycle variation 40mhz 2x_q @ v cc /2 66mhz 80mhz 100mhz t cycle 600ps t cycle 300ps t cycle 300ps t cycle 400ps t cycle + 600ps t cycle + 300ps t cycle + 300ps t cycle + 400ps t pd 2 sync f db k (with 1m w from rc1 to an v cc ) ns sync feedback sync input to feedback delay 66mhz (measured at sync0 or 1 and 80mhz feedback input pins) 100mhz 1.65 1.45 1.25 1.05 0.85 0.65 t skewr 3 (rising) see note 4 outputtooutput skew between outputs q0q4, q/2 (rising edges only) e 500 ps all outputs into a matched 50 w load terminated to v cc /2 t skewf 3 (falling) outputtooutput skew between outputs q0q4 (falling edges only) e 750 ps all outputs into a matched 50 w load terminated to v cc /2 t skewall 3 outputtooutput skew 2x_q, q/2, q0q4 rising, q5 falling e 750 ps all outputs into a matched 50 w load terminated to v cc /2 t lock 4 time required to acquire phaselock from time sync input signal is received 1.0 10 ms also time to lock indicator high t pzl 5 output enable time oe /rst to 2x_q, q0q4, q5 , and q/2 3.0 14 ns measured with the pll_en pin low t phz ,t plz 5 output disable time oe /rst to 2x_q, q0q4, q5 , and q/2 3.0 14 ns measured with the pll_en pin low 1. t cycle in this spec is 1/frequency at which the particular output is running. 2. the t pd specification's min/max values may shift closer to zero if a larger pullup resistor is used. 3. under equally loaded conditions and at a fixed temperature and voltage. 4. with v cc fully poweredon, and an output properly connected to the feedback pin. t lock maximum is with c1 = 0.1 m f, t lock minimum is with c1 = 0.01 m f. 5. the t pzl , t phz , t plz minimum and maximum specifications are estimates, the final guaranteed values will be available when `mc' status is reached. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6 motorola applications information for all versions & $*)%*) d .! (.# #%*) ? the MC88LV915T aligns rising edges of the feedback input and sync input, therefore the sync input does not require a 50% duty cycle. ? all skew specs are measured between the v cc /2 crossing point of the appropriate output edges.all skews are specified as `windows', not as a deviation around a center point. ? if a aqo output is connected to the feedback input (this situation is not shown), the aqo output frequency would match the sync input frequency, the 2x_q output would run at twice the sync frequency, and the q/2 output would run at half the sync frequency. timing notes: (these waveforms represent the hookup configuration of figure 2a on page 7) #%*) (.# #%*) (.#0 1 ?b (.#0 1 figure 1. output/input switching waveforms and timing diagrams d .! k& $*)%*)( -2& $*)%*) & $*)%*) d ( ,8 d ( ,8 d ( ,' d ( ,b d ( ,!! & & $*)%*)( % d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7 motorola figure 2c. wiring diagram and frequency relationships with 2x_q output feed back figure 2b. wiring diagram and frequency relationships with q4 output feed back figure 2a. wiring diagram and frequency relationships with q/2 output feed back & & & 114;*+1- 35:9 7-6:-3,< *3.- = 94 &) & !5-, 8?b '&2(! = 94 &) & !5-, 8?b '&2(! !$, 114;*+1- 35:9 7-6:-3,< *3.- = 94 &) & !5-, 8?b '&2(! = 94 &) & !5-, 8?b '&2(! !$, > d:;c 3@@=;53d;?> d:7 -2& ?ed@ed ;c 5?>>75d76 d? d:7 ;>@ed ):7 ;>d7b>3= %!! g;== =;>7 e@ d:7 @?c;d;f7 7697c ?8 -2& 3>6 (.# d:ec d:7 -2& 8b7ae7>5i g;== 7ae3= d:7 (.# 8b7ae7>5i ):7 & ?ed@ed g;== 3=g3ic be> 3d d:7 -2& 8b7l ae7>5i 3>6 d:7 k& ?ed@edc g;== be> 3d d:7 -2& 8b7ae7>5i 35:9 94 > :95:9 7-6:-3,< -1*90438/05 > d:;c 3@@=;53d;?> d:7 & ?ed@ed ;c 5?>>75d76 d? d:7 ;>@ed ):7 ;>d7b>3= %!! g;== =;>7 e@ d:7 @?c;d;f7 7697c ?8 & 3>6 (.# d:ec d:7 & 8b7ae7>5i 3>6 d:7 b7cd ?8 d:7 k& ?ed@edc g;== 7ae3= d:7 (.# 8b7ae7>5i ):7 & ?ed@ed g;== 3=l g3ic be> 3d d:7 k& 8b7ae7>5i 3>6 d:7 -2& ?ed@ed g;== be> 3d - d:7 k& 8b7ae7>5i 35:9 94 > :95:9 7-6:-3,< -1*90438/05 114;*+1- 35:9 7-6:-3,< *3.- = 94 &) & !5-, 8?b '&2(! = 94 &) & !5-, 8?b '&2(! !$, > d:;c 3@@=;53d;?> d:7 & ?ed@ed ;c 5?>>75d76 d? d:7 ;>@ed ):7 ;>d7b>3= %!! g;== =;>7 e@ d:7 @?c;d;f7 7697c ?8 & 3>6 (.# d:ec d:7 & 8b7ae7>5i g;== 7ae3= d:7 (.# 8b7ae7>5i ):7 k& ?ed@edc & & & g;== 3=g3ic be> 3d - d:7 & 8b7ae7>5i 3>6 d:7 -2& ?ed@ed g;== be> 3d - d:7 & 8b7ae7>5i 35:9 94 > :95:9 7-6:-3,< -1*90438/05 " j ( #! " j ( #! " j ( #! " j ( #! " j ( #! -2& #!$ + '.()! $( !!)$' " j #%*) !$, %!!2# &2(! & & & & & '() ' 2(! (.#0 1 #!$ # ' $ " -)'#! !$$% !)' " j ( #! -2& #!$ + '.()! $( !!)$' " / #%*) !$, %!!2# &2(! & & & & & '() ' 2(! (.#0 1 #!$ # ' $ " -)'#! !$$% !)' " j ( #! -2& #!$ + " j k& !$ $*)%*)( '.()! $( !!)$' " j #%*) !$, %!!2# &2(! & & & & & & '() ' 2(! (.#0 1 #!$ # ' $ " & & -)'#! !$$% !)' " j k& !$ $*)%*)( " j k& !$ $*)%*)( #?d7 8 d:7 $ '() ;>@ed ;c 35d;f7 3 @e==e@ ?b @e==6?g> b7l c;cd?b ;c>d >757cc3bi 3d d:7 @;> c? ;d g?>d g:7> d:7 876 435< ?ed@ed 9?7c ;>d? cd3d7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8 motorola figure 3. recommended loop filter and analog isolation scheme for the MC88LV915T w $ m !$$% !)' % w " w m '& .%(( m !$, '& .%(( w #!$ + ' #!$ # #!$ !$$% !)' +$ () $# $ ) "!+ ) % # %! % #$) ',# )$ (! notes concerning loop filter and board layout issues 1. figure 3 shows a loop filter and analog isolation scheme which will be effective in most applications. the following guidelines should be followed to ensure stable and jitterfree operation: 1a.all loop filter and analog isolation components should be tied as close to the package as possible. stray current passing through the parasitics of long traces can cause undesirable voltage transients at the rc1 pin. 1b.the 47 w resistors, the 10 m f low frequency bypass capacitor, and the 0.1 m f high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88lv915t's sensitivity to voltage transients from the system digital v cc supply and ground planes. this filter will typically ensure that a 100mv step deviation on the digital v cc supply will cause no more than a 100ps phase deviation on the 88lv915t outputs. a 250mv step deviation on v cc using the recommended filter values should cause no more than a 250ps phase deviation; if a 25 m f bypass capacitor is used (instead of 10 m f) a 250mv v cc step should cause no more than a 100ps phase deviation. if good bypass techniques are used on a board design near components which may cause digital v cc and ground noise, the above described v cc step deviations should not occur at the 88lv915t's digital v cc supply. the purpose of the bypass filtering scheme shown in figure 3 is to give the 88lv915t additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1c.there are no special requirements set forth for the loop filter resistors (1m w and 330 w ). the loop filter capacitor (0.1 m f) can be a ceramic chip capacitior, the same as a standard bypass capacitor. 1d.the 1m reference resistor injects current into the internal charge pump of the pll, causing a fixed offset between the outputs and the sync input. this also prevents excessive jitter caused by inherent pll deadband. if the vco (2x_q output) is running above 40mhz, the 1m w resistor provides the correct amount of current injection into the charge pump (23 m a). for the tfn55, 70 or 100, if the vco is running below 40mhz, a 1.5m w reference resistor should be used (instead of 1m w ). 2. in addition to the bypass capacitors used in the analog filter of figure 3, there should be a 0.1 m f bypass capacitor between each of the other (digital) four v cc pins and the board ground plane. this will reduce output switching noise caused by the 88lv915t outputs, in addition to reducing potential for noise in the `analog' section of the chip. these bypass capacitors should also be tied as close to the 88lv915t package as possible. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 9 motorola MC88LV915T system level testing functionality 3state functionality has been added to the 100mhz version of the MC88LV915T to ease system board testing. bringing the oe /rst pin low will put all outputs (except for lock) into the high impedance state. as long as the pll_en pin is low, the q0q4, q5, and the q/2 outputs will remain reset in the low state after the oe /rst until a falling sync edge is seen. the 2x_q output will be the inverse of the sync signal in this mode. if the 3state functionality will be used, a pullup or pull down resistor must be tied to the feedback input pin to prevent it from floating when the fedback output goes into high impedance. with the pll_en pin low the selected sync signal is gated directly into the internal clock distribution network, bypassing and disabling the vco. in this mode the outputs are directly driven by the sync input (per the block diagram). this mode can also be used for low frequency board testing. note: if the outputs are put into 3state during normal pll operation, the loop will be broken and phaselock will be lost. it will take a maximum of 10ms (tlock spec) to regain phaselock after the oe /rst pin goes back high. figure 4. representation of a potential multiprocessing application utilizing the MC88LV915T for frequency multiplication and low boardtoboard skew "!+ ) %!! 8 8 "!+ ) %!! (.()" !$ ($*' %* ' %* ' ""$'. '( ""* ""* ""* ""* ""* %* !$ 8 ""* ""* ""* ""* ""* %* 8 %!! ""$'. $#)'$! !$ 8 ) %$ #) $ *( !$ 8 ) %$ #) $ *( ()' *) !$ 8 "!+ ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10 motorola outline dimensions fn suffix plastic package case 77602 issue d #$)( )*"( ! " # # )'" # , ' )$% $ ! ( $*!' - )( %!() $. ) "$! %') # ! # "#( $# )'* %$( ) $# )$ "(*' ) )*" ) () # %!# "#( $#( ' # * $ #$) #!* "$! !( !!$,! "$! !( ( %' ( "#( $# # # )$!'# # %' #( . " $#)'$!! # "#( $# # ) % )$% ". ("!!' ) # ) % $))$" . *% )$ "#( $#( ' # * ' )'" # ) ) $*)'"$() -)'"( $ ) %!() $. -!*( + $ "$! !( ) ' *''( ) *''( # #)'! !( *) #!* # #. " (") ),# ) )$% # $))$" $ ) %!() $. "#( $# $( #$) #!* "' %'$)'*( $# $' #)'*( $# ) "' %'$)'*( $#( ( !! #$) *( ) "#( $# )$ ')' ) # ) "' #)'*( $#( ( !! #$) *( ) "#( $# )$ ("!!' ) # n m l v w d d y brk view s ( !" ( # ( ) ( !" " # ( ) g1 g j c z r e a !" ( !" " # ( ) t b ( !" ( # ( ) ( !" " # ( ) u ( !" " # ( ) z g1 x view dd ( !" " # ( ) k1 view s h k f ( !" " # ( ) & & " ! ! ( ( # $ % & ' ( f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 11 motorola notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 12 motorola motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operatin g parameters, including at ypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a s ituation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. motorola, inc. 2001. how to reach us: usa/europe/locations not listed : motorola literature distribution; p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 japan : motorola japan ltd.; sps, technical information center, 3201, minamiaz abu. minatoku, tokyo 1068573 japan. 8 1334403569 asia/pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong ko ng. 85226668334 technical information center: 18005216274 home page : http://www.motorola.com/semiconductors/ MC88LV915T/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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